View All Products: Serial Presence Detect (SPD) EEPROMs for DIMMs

1. What is DIMM?

DIMM stands for Dual Inline Memory Module, a memory module with multiple DRAMs and other devices mounted on a printed circuit board.
ABLIC manufactures SPDs (Serial Presence Detectors), which are serial EEPROMs used in these memory modules. Similar to DIMMs, the SPDs are also DDR (Double Data Rate) compliant.
The next section will introduce the latest DDR standard and features related to SPD.

2. Difference between DDR5 and DDR4

DDR5 is a standard set to meet the growing need for efficient performance in a wide range of applications such as PCs and data servers. Therefore, it offers higher bandwidth and capacity than the previous DDR4 standard.
SPD capabilities have also been expanded for system management. The differences between DDR4 and DDR5 are as follows:

Feature	DDR5	DDR4	DDR5 Advantage
Speed	Min 4.8Gbps data rate	Min 1.6Gbps data rate	- Higher Bandwidth
IO Voltage	1.1V	1.2V	- Lower power
Power Management	On DIMM PMIC	On mother board	- Better power efficiency - Better scalability
Channel Architecture	40-bit data channel (32data + 8ECC) 2 channels per DIMM	72-bit data channel (64data + 8ECC) 1 channel per DIMM	- Higher memory efficiency - Lower latency
Burst Length	16	8	- Higher memory efficiency
Max. Die Density	64Gb	16Gb	- Higher capacity DIMMs
More Intelligence	SPD Hub (I3C-Bus) and Temperature Sensor	SPD (I2C-Bus)	- Enhanced system management - Greater telemetry for thermal management

3. Difference between SPD for DDR5 and SPD for DDR4

Compared to the conventional SPD for DDR4, the SPD for DDR5 is characterized by the addition of the I2C-Bus and I3C-Bus interface standards and the Hub function.
These allow SPD for DDR5 to operate at high speeds, contributing to a more robust system management.

Feature	SPD for DDR5	SPD for DDR4	DDR5 SPD Advantage
Interface	I2C / I3C-Bus	I2C-Bus	-
Speed	Max 12.5MHz	Max 1MHz	- Higher speed
IO Voltage	1.0V typ. (I3C-Bus) 3.3V typ. (I2C-Bus)	3.3V typ.	- Lower power
Memory Capacity	8K-bit	4K-bit	- Larger memory capacity
Temperature Accuracy	0.5°C typ. (Ta = +75°C to +95°C)	0.5°C typ. (Ta = +75°C to +95°C)	- No difference
Package	DFN-8	DFN-8	- No difference
Function	Hub function	On mother board	- Enhanced system management
	Packet Error Check (PEC) function	(Nothing)	- Higher noise immunity
	Parity Error Check function	(Nothing)	- Higher noise immunity
	In Band Interrupt (IBI) for Alert function	Event Pin for Alert function	- Needless Event Pin
Application	Combination - for RDIMM, UDIMM, SODIMM (S-34HTS08AB-A8T5U4)	Separation - for RDIMM, UDIMM (S-34TS04A0B-A8T3U5) - for SODIMM (S-34C04AB-A8T3U5)	- All in one

View All Products: Serial Presence Detect (SPD) EEPROMs for DIMMs

4. What is the Hub function?

The DDR5 has more onboard devices for power and thermal management of the system, including a redesigned module configuration.
Therefore, if each device in the module is directly connected to the external controller as in DDR4, there is a problem of increased electrical load on the bus. To address this issue, within the DDR5, the external controller and each device on the DIMM board are connected via SPDs.
This minimizes the electrical load on the module side as seen by the external controller, enabling high-speed operation.

DDR5

Connects an external controller to each device in the module by relaying SPDs.

DDR4

Connects the external controller directly to each device in the module.

The Hub function has been added to SPD to properly manage instructions from the external controller to the device on the DIMM board, while the function of the SPD memory /temperature sensor is operated in the same way as with DDR4. The Hub function solves the communication issues that can arise with bus separation.

5. What is I3C communication?

In DDR5, a Hub function has been added to the SPD to support faster communication, also the communication specification itself has been updated to adopt the I3C communication standard. I3C stands for Improved Inter Integrated Circuits as it is an improved version of the existing I2C (Inter Integrated Circuits).
Although the two-wire connection between SDA and SCL is the same as the I2C communication, the clock speed has been increased from 1MHz to 12.5MHz. With the increased in clock speed, conventional communication noise countermeasures performed by I2C communication have become more difficult. Therefore, I3C employs “The Packet Error Check (PEC) Function” and “The Parity Error Check Function” to detect communication data errors in the communication protocol.

The PEC Function

An 8-bit packet error code (also called PEC) is added at the end of the I3C communication. The error code is calculated by dividing the transmitted data by a specific polynomial. The receiver also divides the transmitted data by a specific polynomial equation, and if the divisor is divisible, the data is considered correct and error-free. In I3C communication, CRC-8 is used for this polynomial.

The Parity Error Check Function

Add a parity bit at the end of each byte of I3C communication (the ACK point in I2C communication). Odd parity is used in I3C communication. If there are an even number of "1"s in a byte, add "1"; if there are an odd number of "1"s, add "0" as a parity bit. The receiver counts the number of "1"s in each byte of the transmitted data, and if the count result is even and the parity bit is set to "1", or if the count result is odd and the parity bit is set to "0", the transmitted data byte is considered correct.

The above functions are only for detecting errors, not for correcting them. Therefore, a function is required for the data receiver to notify the sender of an error.
In the case of DDR4, notification pins and wiring were provided separately from the data lines (ABLIC's SPD for DDR4 had an EVENT pin for temperature sensor alerts). This method required additional separate pins and wiring for each type of notification, which is inappropriate for DDR5, where notification types and the number of devices on the DIMM board are more numerous.

DDR5

Even if the number of notification applications increases, additional terminals and wiring are not required because notifications are performed in the data line.

DDR4

Since terminals and wiring are required for each notification application, additional terminals and wiring are also required when the number of notification types increases.

I3C employs the In Band Interrupt (IBI) function. If there is no activity on the bus for a certain period of time, devices that are in error states (including several state except Packet Error and Parity Error) will initiate communication on their own in response to a start condition issued by HOST. Which device has a higher priority is determined by the communication arbitration.
The data line outputs are compared for each bit, and if there are multiple outputs, the “L” output has priority, and the device with an “H” output stops outputting itself. This arbitration process determines which device has the highest priority.